The invention is generally related to the field of semiconductor devices and fabrication and more specifically to a method for forming a dual damascene structure.
To increase the operating speed, high performance integrated circuits use copper interconnect technology along with low dielectric constant dielectrics. Currently the dual damascene method is the most widely used method for forming copper interconnects. A typical dual damascene process is illustrated in FIGS. 1(a)-1(c). As shown in FIG. 1(a), a first etch stop layer is formed over a dielectric layer 10 and a copper line 20. A first dielectric layer 40, a second etch stop layer 50, and a second dielectric layer 55 are formed over the first etch stop layer. A patterned layer of photoresist is then formed and used to pattern the etching of the first trench 57. Following the etching of the first trench 57, a backside anti-reflective coating (BARC) layer 60 is formed. During the formation of the BARC layer 60, additional BARC material 65 is formed in the trench 57. The additional BARC material 65 is necessary to protect the bottom surface of the trench during the etching of the second trench 58. This is illustrated in FIG. 1(b). A portion of the additional BARC 65 is removed during the etching process. Following the etching of the second trench 58, trench liner material is formed 80 and copper 90 is used to fill both trenches as illustrated in FIG. 1(c).
There are a number of important issues concerning the use of the additional BARC 65 to mask the trench. Some of the more important of these are non-uniformity in dense and isolated structures, punching through the first etch stop layer 30 during the etching process, defects caused by the BRAC material etc. These is therefore a need for an improved process that overcomes the issues associated with the use of the BARC trench masking material 65.
The present invention describes a process for forming dual damascene structures. In particular, a first dielectric layer is formed over a silicon substrate containing one or more electronic devices. A first etch stop layer is then formed over this first dielectric layer and a second dielectric layer is then formed over the first etch stop layer. A silicon oxynitride anti-reflective coating layer is then formed over the second dielectric layer and a first trench is etched to a first depth in the second dielectric layer and the first dielectric layer. A second trench is etched in the second dielectric layer while simultaneously etching the first trench in the first dielectric layer.